With the rapid development of semiconductor technologies, the integrated circuits (ICs) have been developed toward high integration level, high speed and low power consumption. Bulk silicon substrates and bulk silicon devices formed by the bulk silicon techniques are approaching to the physical limitation. Thus, further reducing the critical dimension (CD) of the ICs has met certain challenges. Replacing the bulk silicon substrates and the bulk silicon devices with Silicon-on-Insulator (SOI) substrates and SOI devices is considered as one of the best approaches.
The SOI substrates are used for forming ICs. Comparing with the commonly used bulk silicon substrates, the SOI substrates have some advantages. For example, the ICs formed by the SOI substrates have smaller parasitic capacitances, higher integration level, smaller short channel effect, and faster speed. Further, using SOI substrates is able to achieve dielectric isolations in the devices in the ICs; and the latch-up effect of the ICs is eliminated.
Three-dimensional integrated circuits (3D ICs) are formed by advanced chip-stacking techniques. IC chips with different functions may be stacked into a 3D IC. Comparing with the two-dimensional (2D) ICs, the chip-stacking technique of the 3D ICs not only reduces the signal transmission path of the 3D ICs, but also increases the operation speed of the 3D ICs. Briefly, the stacking technique of the 3D ICs is able to meet certain requirements of semiconductor devices, including better performance, smaller size, lower power consumption, and more functions.
According to the connection methods of the chips in the 3D ICs, the interconnect technique of the stacked-IC chips includes a wire bonding method and a wafer bonding method. The wafer bonding method has a shorter electrical connection path than the wire bonding method; and is able to provide a better thermal property, a better electrical characteristic and a smaller structure size. Thus, the wafer bonding method is one of the most-researched techniques; and is used to achieve a temporary or permanent bonding between different chips.
The bonding type of the wafer bonding method includes the Si—Si direct bonding, the Si-glass static bonding, and the metal-metal bonding. The metal-metal bonding technique is one of the most important research fields. The metal-metal bonding technique bonds two wafers face-to-face by diffusion and/or metal melting between metals and/or between metal and the surface of the wafer through metal and/or metal alloys.
However, in the existing techniques, the electrical properties of the semiconductor structure, after bonding the semiconductor devices formed by the SOI wafer with other substrate or wafer, needs further improvements. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems in the art.